Describe hardware intent. Compile to real silicon.
Forge lets you write FPGA hardware with a modern software workflow — a Rust SDK, a versioned compiler pipeline, and one command to a validated bitstream.
Components that compile all the way down
Every component below is proven from SDK authoring through validated FIR, simulation, and a real, timing-clean bitstream on the iCE40UP5K-SG48 target.
I/O & timing
PinBusClockResetTimerCounterDivider
Storage
RegisterRAMROMFIFO
Logic & arithmetic
ConstantNotAndOrXorMuxAddMultiply
Control & interfaces
StateMachineDebouncePulseTogglePWM
One workflow, from source to bitstream
SDKs describe intent
Rust SDK components, typed connections, and units. No HDL plumbing to hand-write.
Core compiles hardware
Design Schema → FIR → backend, with hostile validation, provenance, and deterministic output at every stage.
CLI orchestrates
forge check, forge verify, forge build — from verified FIR to a packaged target bitstream.
Community stays genuinely useful
Check, verify, inspect, trace, and build community-tier targets — free, forever. Paid editions add commercial and enterprise capability, not artificial limits.